1. Field of the Invention
The present invention relates to a method of estimating a complexity degree of signal wirings in a semiconductor integrated circuit and, more particularly, the technology that is capable of estimating a complexity degree of wirings used to connect integrated circuits with high precision at an early stage to define an available space of the integrated circuit.
2. Description of the Related Art
Recently the semiconductor integrated circuit (referred to as an “LSI” hereinafter) is incorporated into various products. In order to clarify a development cost of LSI, a space of LSI (referred to as a “chip size” hereinafter) must be defined at the earliest possible stage of layout design. In order to define the chip size, physical placement positions in the integrated circuit must be decided, then power-supply wirings for supplying a power must be laid, then wirings for connecting the integrated circuits (referred to as “signal wirings” hereinafter) must be connected, then an available space including up to physical wiring spaces must be checked.
Meanwhile, in order to check the available space including up to the physical wirings, the process must go ahead to the signal wiring stage in LSI design. In some cases a wiring complexity due to a lack of wiring space is caused at last locally or totally at the final stage. At that time, such a situation sometimes occurs that the layout design must be carried out once again from the beginning. By the way, as the method of checking the complexity degree at the time of laying the wirings, there exists the approach of dividing the inside of LSI into plural lattices after the integrated circuits are placed, then applying virtual wirings to connect the integrated circuits at a shortest distance, and then checking how many wirings are present in respective lattices (see Patent JP-A-5-174091).
As seen in JP-A-5-174091, the approach in the prior art checks whether or not a space necessary for the signal wirings are assured, by applying the automatic placement of the integrated circuits and then laying the virtual signal wirings in the LSI layout step. Such approach is effective when a wiring space required to supply a power to the integrated circuits is small and also a time required to lay the power supply wirings is negligibly small rather than a time required for the placement and the virtual wiring provision.
However, a scale of the integrated circuit is increased in the recent LSI. Accordingly, a space required to lay the power-supply wirings for supplying a power to insides of the circuits tends to increase remarkably. Also, a design term required to lay the power-supply wirings also tends to increase remarkably with an increase of the power-supply wiring laying space.
Under such circumstances, even though a space necessary for all wirings is estimated only based on the space required for the signal wirings without regard to the wiring spaces that are needed to supply the power to the integrated circuits as an LSI space including the wirings, a space enough to lay the signal wirings cannot be secured when the signal wirings are provided after the step goes finally to the laying of the power-supply wirings. This is because a space error caused to pay no regard to an increase of a power-supply wiring space is generated. Thus, such a problem has arisen sometimes that the modification of the placement positions of the integrated circuits or the modification of the chip size must be made.
Also, if it is intended to estimate a complexity degree of the signal wirings after the laying of the power-supply wirings were completed, a time required for one-time provision of the power-supply wirings is increased as described above. Therefore, a lot of times are consumed until the estimation of a wiring complexity degree is carried out after the power-supply wirings were laid and then the signal wirings were connected. Also, according to the result of the complexity degree, such a situation is supposed that modifications such as a modification of the integrated circuit placement, and the like should be applied. At that time, a term to lay the power-supply wirings is needed once again, and thus such a problem existed that a term required to define the LSI space is prolonged.
However, assume that a space required for laying the power-supply wirings can be forecasted previously, a complexity degree of the signal wirings can be estimated with good precision before the power-supply wirings are laid actually if the wiring space required for laying the power-supply wirings is deleted automatically in advance from the wirable space of the signal wirings. According to this, a term required to estimate a wiring complexity degree can be reduced. In other words, the conventional approach is uncertain in checking whether or not the layout design can be carried out within the present LSI space with regard to the signal wiring space. Thus, in some cases a term required until the complexity degree can be estimated is increased excessively.